Design Control & Creation	Altair PollEx, SVN and ClioSoft, Altium Designer, Autodesk EAGLE, EasyEDA, Cadence Virtuoso
Document Control	Microsoft SharePoint,
Requirements Capture	Sparx Systems Enterprise Architect
Regression	Jenkins/ Cadence vManager
System Design	Mathworks Matlab / GNU Octave, Excel, Verilog
Analog Environment	Cadence Virtuoso IC (Composer, ADE-XL, LayoutXL)
RF/Analog/MS Simulation	Cadence Spectre/ MMSIM, Mentor AFS/Symphony, Keysight ADS
Electro-Magnetic simulation	Keysight RFpro, Momentum & FEM, Ansys HFSS
Digital Simulation	3DS SIMULIA, Active-HDL, Mentor Questa, Cadence Xcelium Simulator, Silvaco
Verification planning	MS Excel / Cadence vManager
Linting / CDC	Questa CDC, Cadence HAL
Synthesis	Synopsys Design Compler Ultra & Cadence Genus Synthesis Solution, Xilinx
UPF Verification	Synopsys Verdi Suite
Place & Route	Cadence Innovus and Synopsys IC Compiler II
DFT	JTAG. Mentor Tessent
Layout Extraction	Mentor Calibre PEX (analog), Synopsys StarRC (digital)
Digital Sign-off Timing	Synopsys PrimeTime
Power/Thermal Analysis	Cadence Voltus
Logic Equivalence	Synopsys Formality and Cadence Conformal
Physcial Verification	Mentor Calibre DRC/ERC/LVS
PCB Design and layout	Altium Designer
Yield Analysis	YieldHUB
Security Testing	Synopsys
Design Rule Check	Tanner EDA